Clock & tick
A clock edge is the moment state updates. One tick here means one modeled edge, not a measured duration on a board.
FPGA thinking for software developers
From Software
to Silicon.
Describe circuits that work together, and learn how their timing changes the way you build software.
Explore streaming data, chip-level parallelism and software-controlled experiments, then study how inference and learning systems divide work between circuits and software. Begin in your browser; a board can come later.
Start the foundationsWork is stored in this browser on this address. Export to keep a portable copy.
CIRCUITS TO SYSTEMS · READ, PREDICT, EXPLAIN
Think in circuits.
A circuit describes what is connected and how state changes. These lessons build the vocabulary for the experiment below.
Choose a route through the course.
These are planning estimates, not measured completion times. Shorter routes have narrower outcomes. All lessons remain open, and optional deep dives can take longer.
CONCEPTUAL EXPERIMENT · ABOUT 10–15 MINUTES
Where did the events go?
A signal source keeps producing events while software reads more slowly. Predict what a small queue can retain, then inspect every edge.
Trigger & capture
The trigger starts recording at a chosen tick. Each later pulse inside the capture window attempts to store one event.
FIFO
A first-in, first-out queue sends the oldest record first. Ours has a fixed capacity. When full, it drops the newest arrival.
Read the exact rules before predicting
- The tick begins at 0. Step processes tick 1 first.
- At each edge the host reads one old record if the tick is divisible by its read interval. A read of an empty queue does nothing.
- The trigger starts capture on its own edge. The source pulses on multiples of the event interval.
- Capture lasts the chosen number of edges, including the trigger edge. An event on its final edge still counts.
- Each attempted event gets a sequence number starting at 0, even if it is dropped. A full queue drops the new arrival.
- The 8-bit timestamp is tick modulo 256. Host reads continue after capture stops.
Read-before-write and drop-newest are choices in this original teaching model. They are not universal FPGA behavior.
EVENT RECORDER / MODEL 01AWAITING PREDICTION
3 / RUN & INSPECT
The waveform and result appear after you commit. A prediction is a hypothesis, not a score.
Tick—
Attempted—
Dropped—
Received—
Commit your prediction to start the clock.
Scroll the waveform horizontally for later ticks. The event log lists every edge.
Stepping and replay change a JavaScript model. No HDL simulator or board is connected.
Inspect the event log (text alternative to the waveform)
| Tick | Timestamp | Action | Pending |
|---|
Repair the capture
Make a new prediction with the same event source and capture window. Change only the FIFO capacity or host read interval to keep every event. Use the log to explain which edge your change fixes.
Inspect a sequence gap
A missing sequence number is evidence that a record did not arrive. The drop counter narrows the explanation in this model. A real connection can also lose or corrupt data elsewhere.
Explain the limit
Pause host reads with interval 0 and lengthen the capture. Why does increasing capacity postpone overflow rather than remove the rate mismatch?
APPLY THE IDEAS · FIRST ATTEMPTS ARE RETAINED
Different cases. Same reasoning.
Use the ideas of bounded storage, counter width and accepted transfers. Hints are optional and recorded. These checks do not lock the course.
Choose an open-ended challenge, or download the 15 foundation exercises and nine timing, crossing and memory challenges, plus six application challenges and six RL, verification and agent challenges, plus four inference and feasibility challenges. Read the practice and fast-route guide.
DESIGN, TRACE & EXPLAIN · UNGRADED
Put the reasoning in your own words.
The transfer tasks offer a fast route if the fundamentals are familiar. Write your answer before consulting a reference. Saved responses can be exported for review; this page does not grade prose.
The workbook questions are loading. The download above is available if they cannot load.
THE COURSE MAP
From a signal to a system.
Each module shows its readiness. Physical projects are optional companions.
KNOW WHAT YOUR EVIDENCE ESTABLISHES
Four different kinds of “works.”
Conceptual model
The browser executes our declared rules. It helps reason about state, ordering and bounded storage. It cannot validate a hardware description.
HDL simulation
A simulator executes Verilog or SystemVerilog against a testbench. Python and cocotb can drive checks. Those tests still depend on their coverage and assumptions.
Synthesis & timing
Tools map logic onto FPGA resources and check constraints. A passing behavioral test does not establish resource fit or timing closure.
Physical board
A board test exercises the actual clock, pins, interface and connected hardware. Nexys Video revision, cables, Windows tools and physical operation remain unverified here.
Read the source material
Lessons, code and diagrams are original teaching material informed by these references. Links are not claims that a source implements this model. No third-party project code is bundled.
Acknowledgment
Thanks to rothej for sharing public FPGA work that helped inform this course, including the FPGA CI/CD toolchain demo and its Python-based verification approach.