# Foundation workbook

Choose the ordinary route or the optional challenge route described in `assessment-routes.md`. These are written practice tasks, not an automatically graded mastery test. Keep the first answer, revisions and any help used. Transfer tasks have no hints.

## f1-complete: Complete a capture trace

Lesson: circuit-and-host; objective: FSC-01; type: completion; version: 2.

Reset the conceptual recorder. Set triggerAt=3, duration=7, eventEvery=2, drainEvery=0 and depth=2. Before running, write the first capture tick, all attempted capture ticks, the final queue sequence numbers, and the number of drops. Then step through tick 9 and compare.

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## f1-account: Find a missing suffix

Lesson: circuit-and-host; objective: FSC-01; type: practice; version: 2.

Under the recorder contract, sequence numbers start at 0 and count every attempted capture. A completed run reports attempted=6, dropped=2 and four received records numbered 0,1,2,3. The queue is empty, with no reset, wrap or losses outside the FIFO. A reader calls this a complete capture because no sequence gap is visible. Explain the error and identify the missing attempt numbers.

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## f1-transfer: Preserve a player’s rhythm

Lesson: circuit-and-host; objective: FSC-02; type: transfer; version: 2.

A DIY drum controller receives clean pad-edge signals at ticks 11 and 16. Its queue has room for both, but its browser pauses and receives the records at ticks 31 and 32. All times use one model clock, with no wrap or loss. Design where to attach timestamps, where to edit drum names, and what fields the controller sends. Give the original edge spacing and explain why replaying the arrival spacing changes the rhythm.

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## f2-table: Finish a control predicate

Lesson: bits-and-decisions; objective: FSC-04; type: completion; version: 2.

An alarm should be active when enabled=1 and at least one of empty or clock_missing is 1. Write the output for input rows (enabled,empty,clock_missing): 000,001,010,011,100,101,110,111. Then write the Boolean expression. Treat clock_missing as an already supplied input.

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## f2-width: Specify the spare codes

Lesson: bits-and-decisions; objective: FSC-06; type: practice; version: 2.

A palette has 25 entries numbered 0–24. Choose the smallest unsigned binary index width. Name the unused codes and propose deterministic behavior if the host sends one.

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## f2-transfer: Two fields, one bit pattern

Lesson: bits-and-decisions; objective: FSC-06; type: transfer; version: 1.

A packet contains two bytes, both 11110110. The first is defined as signed two’s-complement audio; the second is an unsigned status bitmask. A host library decodes both as signed integers and calls this a simplification. Explain the problem and give the intended numeric interpretations.

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## f3-edges: Keep old and new columns

Lesson: clocks-and-state; objective: FSC-07; type: completion; version: 2.

Use the lesson’s count/captured RTL. Start at count=7,captured=3. Apply three edges with (reset,event_present) = (0,0),(0,1),(1,1). Write both stored values after each edge.

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## f3-wrap: State the missing bound

Lesson: clocks-and-state; objective: FSC-08; type: practice; version: 2.

Two eight-bit stamps are 252 and then 7. Compute elapsed ticks if the interval is known to be shorter than 256 ticks. Then give a different nonnegative elapsed interval that fits the same stamps when that bound is removed, and explain the ambiguity.

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## f3-transfer: Include the start, exclude the stop

Lesson: clocks-and-state; objective: FSC-09; type: transfer; version: 2.

A loop recorder has WAITING, RECORDING and COMPLETE states. Use the state before the edge. In WAITING, start=1 enters RECORDING. An event on that start edge must be captured. While RECORDING, later events are captured. stop=1 suppresses capture on that edge, even if start=1. COMPLETE never captures, and reset is absent. Write capture_now using state, start, stop and event_present. Evaluate it for (WAITING,1,0,1), (RECORDING,0,1,1) and (COMPLETE,1,0,1), where each tuple is (state,start,stop,event_present). Explain the error in testing only state==RECORDING.

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## f4-stall: Hold the item until acceptance

Lesson: queues-and-flow; objective: FSC-10; type: completion; version: 2.

A source has items A,B,C. Across five edges, ready is 0,1,1,0,1; valid stays 1. The source follows discrete-item ready/valid rules. Give the item on the data signals at each edge and the accepted sequence.

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## f4-account: Account for every attempted record

Lesson: queues-and-flow; objective: FSC-11; type: practice; version: 2.

A run starts with an empty queue and zero counters. It records attempted=10, dropped=3 and delivered=4, with no reset or other loss path. Compute accepted and still queued. Explain why attempted−delivered alone is not queue occupancy.

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## f4-transfer: Reserve space for live events

Lesson: queues-and-flow; objective: FSC-12; type: transfer; version: 2.

A music accessory has a shared storage pool of six record slots. Host-sent preset commands can wait before admission; clean physical pad-edge events cannot. The event contract allows at most three pad events between occasions when the host drains all pending events. Design an admission policy that preserves every event within this bound while presets are busy. State how many slots must remain available for events, what may wait, and what the host must see if a fourth event arrives before a drain.

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## f5-decode: Decode the contract

Lesson: test-and-connect; objective: FSC-14; type: completion; version: 2.

A two-byte unsigned value arrives as bytes 0x12,0x34. The protocol says low byte first. Compute the value in hexadecimal and decimal. Then state what additional parser state is needed if the first read returns only 0x12.

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## f5-cost: Include the boundary

Lesson: test-and-connect; objective: FSC-15; type: practice; version: 2.

For one small request, software takes 30 microseconds. The device route takes 12 microseconds transfer in, 4 compute, 11 transfer out and 7 host overhead. Compare complete latency and state one different benefit that could still justify exploring a circuit.

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## f5-transfer: Review a claimed success

Lesson: test-and-connect; objective: FSC-13; type: transfer; version: 2.

A report says: “The browser graph is smooth, the RTL passed one constant-input simulation, and synthesis completed, so our board records every event at the requested clock.” Give three missing checks spanning function, implementation timing and physical operation. Tie each to the unsupported claim. For the functional check, specify actual stimuli and expected observations, not just a tool name. State one operating bound that an honest “every event” claim needs.

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