# Advanced foundation workbook — modules 6–8

These are conceptual tasks for a programmer learning hardware design. Start with the transfer task if the earlier practice is already comfortable. Use the guided and debug tasks for a specific gap. Keep first answers and assistance separate. No task requires a tool installation or board.

## a06-cuts: Separate clock period from item latency

Module m06; objective FSC-16; completion; version 1.

A toy pipeline has ordered operations P=2 ns, Q=4 ns, R=3 ns, S=1 ns. Each stage adds a 1 ns allowance. Compare the partitions PQRS, PQ|RS and P|Q|RS. For each, give the minimum permitted period and latency when operated at that minimum period. Assume no stalls and latency = number of stages × period.

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## a06-elastic: Trace simultaneous leave and replace

Module m06; objective FSC-17; practice; version 1.

Use the lesson’s one-item elastic stage, initially empty, with reset=0 throughout and no bypass. The source offers A,B,C in order and holds each until accepted. It deasserts in_valid after C is accepted. Across edges 1–5, out_ready is 1,0,1,1,1. For each edge, list any output transfer, any accepted input and the item/full state after the edge. Explain why ready=1 on edge 1 does not send A straight through.

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## a06-transfer: Meet the stream contract with a defensible pipeline

Module m06; objective FSC-16; transfer; version 2.

An agent-controlled sensor preprocessor applies ordered operations P=1 ns, Q=2 ns, R=4 ns, S=3 ns. A stage may contain only consecutive whole operations, and adds a 1 ns allowance. It must run on a fixed 6 ns clock with at most three stages. Choose cuts, give the minimum period allowed by your cuts, and give unstalled item latency at the actual 6 ns clock. A record contains both value and request ID. State how these move during stalls. Finally, if backpressure is delayed by one edge while the source may send one extra record, explain the additional capacity required. All delays are fictional.

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## a07-wire: Price every transmitted bit

Module m07; objective FSC-19; completion; version 1.

A hypothetical UART sends 8N1: 1 start, 8 data and 1 stop bit per byte. The wire rate is 960,000 bits/s. A complete record is 24 transmitted bytes, including all headers. Compute its ideal record-rate ceiling. The producer requires 4,800 records/s continuously. Explain whether a faster internal FPGA clock alone fixes the gap.

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## a07-toggle: Expose the missing event count

Module m07; objective FSC-21; practice; version 1.

A source toggles a bit once per event. The destination observes 1, then later 1 again. There were at most four events between observations. List every possible event count consistent with these observations. Give two distinct source histories that produce the same destination observations, then explain what an acknowledged event protocol must prevent.

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## a07-transfer: Design the agent-to-device boundary

Module m07; objective FSC-21; transfer; version 1.

A software agent occasionally changes a device’s gain word and enable bit; both must take effect together. The device emits 16-byte records at 2,000 records/s. A hypothetical return link is 1,000,000 bits/s with 8N1 and no other wire overhead. During a supported host pause, at most 30 new records arrive and four are already queued; none leave. Commands may wait, but captured events may not. Specify coherent command transfer across unrelated clocks, calculate the ideal link ceiling and required queue capacity for that pause, and state what must happen if the bound is exceeded. Do not claim analog CDC safety from a browser or digital trace.

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## a08-layout: Distinguish packed data from a chosen layout

Module m08; objective FSC-22; completion; version 1.

A table stores 1,000 unsigned values of 10 bits each. Give its packed data size in bits and bytes. Then give storage bytes if each value instead occupies one 16-bit word. State why neither number alone proves the table fits a particular FPGA memory resource.

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## a08-collision: Trace the specified read/write mode

Module m08; objective FSC-23; practice; version 2.

Use the lesson’s uncompiled RTL fragment. Initially mem[2]=5 and mem[7]=11. At edge1 addr=2,wr_en=1,wr_data=9. At edge2 addr=7,wr_en=0. At edge3 addr=2,wr_en=0. Give rd_data after each edge and the final values of mem[2] and mem[7]. Explain why this source-level trace does not establish a particular physical RAM’s collision mode.

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## a08-transfer: Find the memory limit in a tiny-model engine

Module m08; objective FSC-23; transfer; version 1.

A toy inference engine evaluates independent items. Each item requires two reads from a read-only coefficient table and one write to a separate result memory. The coefficient memory provides one word read per edge; the result memory independently provides one write per edge. Four arithmetic lanes each have enough compute capacity for one item per edge, but there is no coefficient reuse and every read request can name any address. Compute the aggregate item-rate ceiling in items/edge. How many replicated single-read-port coefficient memories would supply just the coefficient bandwidth for four items per edge? After that replication, state whether the unchanged result port permits four completed items per edge. The table has 1,024 entries of 16 bits. Compute coefficient data bits across those copies, and describe how a host update avoids mixing old and new coefficients in one item. All ports are ideal; no device fit or timing claim is requested.

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