# Advanced foundation workbook — modules 15–16

These are conceptual tasks for a programmer learning hardware design. Start with the transfer task if the earlier practice is already comfortable. Use the guided and debug tasks for a specific gap. Keep first answers and assistance separate. No task requires a tool installation or board.

## a15-numeric: Keep products, widths and real values consistent

Module m15; objective FSC-44; practice; version 1.

Use x=[−3,2,1,−2] and weight rows [1,2,−1,1] and [−1,1,2,0]. List each row’s four products, integer score and selected index. Ties select index 0. Inputs and weights may each use the entire signed four-bit range −8…7; there is no bias. Derive the possible range of a four-product sum and the minimum signed accumulator width. With input scale 0.25 and weight scale 0.5, both with zero offsets, give the real scores. In a separate case, raw output scores are [12,8] with respective positive scales [0.0625,0.125]. Does the larger raw integer identify the larger real score?

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## a15-transfer: Choose a score schedule at the complete request boundary

Module m15; objective FSC-45; transfer; version 1.

A batch contains 16 four-element vectors and two weight rows. Load eight padded weight words once for the batch; each vector then loads four words and returns two score words. All word transfers take 2 ns each. A one-MAC design uses eight compute cycles/vector at 10 ns/cycle; a two-MAC design uses four at 12 ns/cycle; an eight-multiplier tree uses three at 20 ns/cycle. These are stipulated hypothetical durations, with enough operand service for each listed schedule. No transfers, vectors or compute stages overlap. Count numeric payload only; tag, selected-index and framing costs are stipulated zero in this toy budget and need separate measurement in an implementation. Host-only software costs 80 ns/vector with the same outputs. Calculate each complete batch cost and average per vector, choose the fastest complete path, and explain why lane count alone does not choose it. State what changes if only one fresh operand pair can be supplied per compute cycle with no reuse. Specify model-version/tag handling and two correctness tests, including a tie, before accepting a faster implementation.

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## a16-cache: Budget KV heads, batch and precision separately

Module m16; objective FSC-47; practice; version 1.

A simplified cache has four layers, 128 retained tokens per request, two KV heads, head dimension 16, two bytes per element and batch size three. There are eight query heads; only the stated two KV heads are stored. Calculate cache payload bytes and KiB, using 1 KiB=1,024 bytes. Raw weights are 262,144 parameters at four bits; reserve another 32 KiB for activations. Does their combined payload fit a 320 KiB budget? Then recompute the combined total for a proposed one-byte cache format with all other dimensions unchanged. State what these capacity calculations cannot establish about that precision change.

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## a16-transfer: Separate a bandwidth ceiling from a feasible decoder path

Module m16; objective FSC-48; transfer; version 1.

A hypothetical batch-one decoder design has 6,000,000 four-bit weights. Available device payload storage is 2,000,000 bytes, of which 128 KiB is reserved for cache and activations. Propose a weight-tiling plan that fits. Assume exactly the full raw weight payload crosses a sustained 150,000,000-byte/s path for every token, with no reuse or compression. Other work costs 4 ms compute and 3 ms cache/control per token; nothing overlaps. Calculate raw weight bytes, the weight-traffic-only token-rate ceiling, and the complete stated per-token latency/rate. Does it meet a target of at least 40 tokens/s or beat a correct host baseline of 24 ms/token? Explain what a faster isolated projection experiment would and would not establish about this complete design.

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