AI & engineering · 16 modules · Free
From Software to Silicon
A circuit keeps producing data while software pauses. Decide what belongs on each side, then test the consequences.
Start the courseWhat you’ll work through
- Clocks, state, timing, queues and memory.
- Software interfaces, streaming systems and bounded inference experiments.
- Predictions, traces and design arguments with original attempts preserved.
Before you start
Comfort reading code and tests. No prior FPGA experience, board, installation, account or paid service is needed for the browser course.
Choose a main route planned for about five hours or a shorter route with narrower outcomes. Times are author estimates, not measured learner results. Physical projects are optional.
Browser models teach declared concepts. They are separate from HDL simulation, timing closure and physical board verification. Export your work to keep a copy.
Source: one event every 2 ticks.
Host: one read every 5 ticks.
Queue: three records.
Which event is lost first?
Predict, run, inspect.
Explain what the trace establishes.